An Area-Efficient Bit-Serial Integer Multiplier
نویسندگان
چکیده
This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers. It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [6,7]. The multiplier operates least significant bit (LSB)-first. It is a modular bit-serial design which on the one hand can be efficiently implemented in hardware and on the other hand has the advantage that it can handle operands of arbitrary length.
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